Method for manufacturing wafer level chip size package

ABSTRACT

A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for manufacturing awafer level chip size package (WLCSP) and, in particular, to a methodfor manufacturing a wafer level chip size package having lead frame withredistribution lead fingers and using drilling and filling, instead ofwire bonding or bumps, for inner electrical connection.

[0003] 2. Description of the Prior Art

[0004] Packages in the same size of, or slightly larger than the chipsthey pack are always called chip size package, CSP. The size of thepackage is not larger than 1.2 times of size of the chip and meets therecent demand of electronic component being thin and small. Comparing toboth bare chip and flip chip, chip size package has better protection toresist dust and humidity.

[0005] To simplify manufacturing process of chip size package, a waferpackage is claimed in EP patent No. 0844665. A lead frame is used asinterposer of the chip size package and process of packaging proceedsdirectly on a wafer having a plurality of chips. For the out connectersof lead frame can only being formed on the perimeter of the chip,therefore, there is no way this method can pack wafer havingmulti-electrodes. And, for using bonding wire as inner connector betweenlead frame and chip by wire bonding, wire bonding machine in the backprocess has to be moved to wafer process on the pre process, and that isnot proper for process integration.

[0006] A well-known method for wafer level package in accordance withU.S. Pat. No. 6,022,738 discloses a technique to drill blind hole on theisolative package body of the pre-sealed wafer, and provide metalcoating traversing the package body for plating solder bumps. Thedrawback is that the wafer has to place redistribution circuits andplace the connecting pads in a proper position, so that the method forwafer package cannot be applied in a wafer having different distributionof connecting pads.

SUMMARY OF THE INVENTION

[0007] Therefore, the first object of present invention is to provide amethod for manufacturing the wafer level chip size package which packageon the wafer directly, in particular, directly package on wafer havingdifferent type of connecting pads distribution or multi-electrodes.

[0008] The second object of present invention is to provide a method formanufacturing the wafer level chip size package, which selectively etchthe first layer of a metal plate to form the redistribution conductivecircuits, drill blind holes after securing metal and wafer, andelectrically connect connecting pads of wafer and conductive circuits ofmetal plate by filling conductive material into blind holes, thus chipsize packages having multi-electrodes can be produced.

[0009] The third object of present invention is to provide a chip sizepackage, wherein, the redistribution conductive circuits of the chipsize package having the first ends and the second ends, wherein, thefirst ends being at vertical position with connecting pads of chip, andacting as inner electrical connection of the package structure toreplace bumps or bonding wire by drilling and traversing the first endsafter encapsulating.

[0010] The forth object of present invention is to provide a method togrow bumps on wafer, wherein proceed packaging wafer with metal plate(lead frame) and redistribute out connecting points simultaneously, thuscan package wafer having different connecting pads and eliminate processof redistribution in wafer.

[0011] According to the method for manufacturing a wafer level chip sizepackage, the steps of the method comprises:

[0012] providing a wafer having a plurality of chips, each chip having aplurality of connecting pads on its active surface;

[0013] providing a metal plate consisting of the first layer and thesecond layer, wherein, a plurality of conductive circuits being formedby selectively etching the first layer of the metal plate, the pluralityof conductive circuits being fixed on the second layer of the metalplate, and individual conductive circuit having at least the first endand the second end, and the first ends corresponding to the distributionof connecting pads of chips in the wafer;

[0014] securing active surface of the wafer to the first layer of themetal plate, when the wafer and the metal plate being secured,connecting pads of the chips and the first ends of the conductivecircuits being in vertical position to each other;

[0015] drilling blind holes on the plurality of first ends, wherein theblind holes traversing through metal plate and expose connecting pads ofthe wafer;

[0016] filling conductive material on the plurality of blind holes untilthe connecting pads of chip and the first ends of the conductivecircuits becoming electrical connection;

[0017] removing the second layer of the metal plate;

[0018] planting solder balls on the second ends of the conductivecircuits; and

[0019] dicing the packed wafer and resulting in a plurality of chip sizepackages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a perspective view showing a well-known wafer;

[0021]FIG. 2 is a perspective view showing distribution of connectingpads of a chip in a wafer;

[0022]FIG. 3 is a perspective view showing a lead frame of the metalplate corresponding to a chip according to the present invention;

[0023]FIG. 4 is a cross-sectional view showing the secured structure ofwafer and metal plate according to the present invention;

[0024]FIG. 5 is a cross-sectional view showing the secured structureafter laser drill according to the present invention;

[0025]FIG. 6 is a cross-sectional view showing the secured structureafter coating according to the first embodiment of present invention;

[0026]FIG. 7 is a cross-sectional view showing the secured structureafter filling conductive material according to the present invention;

[0027]FIG. 8 is a cross-sectional view showing the secured structureafter grinding according to the first embodiment of present invention;

[0028]FIG. 9 is a cross-sectional view showing the secured structureafter plating solder ball according to the present invention;

[0029]FIG. 10 is a cross-sectional view showing one of chip sizepackages after dicing according to the present invention;

[0030]FIG. 11 is a cross-sectional view showing one of chip sizepackages secured to circuit board according to the present invention;

[0031]FIG. 12 is a cross-sectional view showing one of chip size packagesecured to circuit board having ability of peeling off according to thepresent invention;

[0032]FIG. 13 is a cross-sectional view showing another chip sizepackage according to the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0033] Referring now to the drawings, the chip size packages accordingto the individual embodiments of the present invention will bedescribed.

[0034] The method for manufacturing process of a wafer level chip sizepackage according to the embodiment of the present invention comprisesthe following steps.

[0035] As shown in FIG. 1, in step of providing a wafer 100, wherein,the wafer 100 generally is sliced from monosilicon crystal ingot orpolysilicon crystal ingot and then integrated circuit layout is formedon its surface. The wafer 100 comprises a plurality of chips 110 anddice area 120 is reserved between chips 110 for cutting the wafer 100into a plurality of individual chips 110 after forming integratedcircuits. As shown in FIG. 2, each chip has a plurality of connectingpads 111 on the active surface of the wafer 100 as its outer connectors.In this embodiment, a chip 110 has generally distributed connecting pads111. Connecting pads 111 are near perimeter of active surface of thechip 110, arranged closely to each other, used for the well-known methodof wire-bonding and securing to the adjacent lead fingers or substrate .Generally speaking, pitch between connecting pads 111 of the chip 110 isvery tiny (about 40 to 100 μm) and it is not suitable to form bumps onthe connecting pads for flip chip securing to the circuit boarddirectly.

[0036]FIG. 3. shows step of providing a metal plate 200 as lead framefor the wafer 100. It is better that selecting an alloy that itscoefficient expansion is near to the wafer 100 for the meatal plate 200.Wherein, the metal plate 200 consists of the first layer 211 and thesecond layer 212 (referring to FIG. 4). To strengthen adherence withadhesive 300, the first layer 211 of metal plate 200 better has a roughsurface. There is an area 213 on the metal plate 200 corresponding tothe said plurality of chips 110 of wafer 100, wherein, in acorresponding area 213, the first layer 211 of metal plate 200 is usedas lead frame 220 of chip size package of the chip 110.

[0037] Then, shown in FIGS. 3 and 4 is step of selectively etching thefirst layer 211 of the metal plate 200 to form a plurality ofredistribution conductive circuits 221 (or lead fingers). The secondlayer 212 of the metal plate 200 supports the plurality ofredistribution conductive circuits 221. That is, the plurality ofredistribution conductive circuits 221 protrudes from and also supportedby the second layer 212 of the metal plate 200. Etch the first layer 211of the metal plate 200 and leave only conductive circuits 123. Since theplurality conductive circuits 221 are supported by and shaped in onewith the second layer 212 of the metal plate 200, there will be nocircumstance of shifting or falling off, and far more stable than usingsurrounding dam bar to connect and fix lead fingers of well-known leadframe. The conductive circuits 221 are of different length and in anydemanded curve shape. Using well-known technique, such as using a maskto cover path for the conductive circuits 221 of the first layer 211 ofthe metal plate 200, and then proceed selectively etching, can form theconductive circuits 211. The plurality of conductive circuits 221 allhas respective connected first end 222 and second end 223. The firstends 222 are corresponding to the connecting pads 111 of the chip 110and near perimeter of the corresponding area 213 for inner electricalconnection with the connecting pads 111 of the chip 110. The meaning of“redistribution” is that the second ends 223 distribute over thecorresponding area 213 to provide outer electrical connection of chipsize package and the minimum distance between a plurality of the secondends 223 is longer than the minimum distance between a plurality of thefirst ends 222 (referring to FIG. 3). For adjacent second ends 223distributing more dispersedly and evenly than adjacent first ends 222doing, outer electrical connection of the chip 110 leans on the secondends 223 of the conductive circuits 221 to redistribute its layout.Besides, the conductive circuits 221 can also be seen as lead fingers oflead frame of chip size package.

[0038]FIG. 4 shows securing active surface (surface having connectingpads 111) of said wafer 100 to the first layer 211 of the metal plate200 mechanically. When the wafer 100 and the metal plate 200 beingsecured, connecting pads 111 in chip 110 and the first ends 222 ofconductive circuits 221 are corresponding to each other vertically. Inthis embodiment, when securing wafer 100 and metal plate 200 withinsulating adhesive 300, normally there is a insulating material (filledby adhesive 300) left between the first ends 222 of metal plate 200 andconnecting pads 111 of wafer 100, and that don't assure of electricallyconnecting both certainly, especially forming a insulating layer betweenwafer 100 and metal plate 200. Besides, the insulating material used asadhesive 300 for securing wafer 100 and the metal plate 200 is liquidepoxy compound or other adhering combination material, such as solidpolyimide tape, film and substrate. If use liquid epoxy compounds asadhering material, a curing process is needed to solidify the adhesive300. Particular things to know is that, in this step, the wafer 100 andthe metal plate 200 are not electrically connected; further, adhesive300 isolate the wafer 100 and the metal plate 200.

[0039]FIG. 5 shows laser drill blind holes 224 on a plurality of firstends 222. A method of controlled depth drilling is used to process thisstep. Wherein, depth of a blind hole 224 is enough to traverse metalplate 200 and adhesive 300, and then expose connecting pads 111 of chip110. Diameter of blind hole 224 is better to be smaller than diameter ofcross-sectional area of the first end 222. That is, the blind hole 224is formed inside the first end 222 to increase electrical connectionarea between conductive circuit 221 and connecting pad 111.

[0040]FIG. 6 shows coating metal foil 225 on said blind holes 224.Generally, the methods are to electroplate nickel, copper, or to depositmetal film during PVD (Physical Vapor Deposition) or CVD (Chemical VaporDeposition) process of wafer manufacturing, or method similar to UBM(Under Bump Metallization) manufacturing. Then, as shown in FIG. 7,filling conductive paste 226 to blind holes 224 for electricalconnection of connecting pads 111 of chips 110 in the wafer 100 andconductive circuits 221, wherein, the conductive paste 226 is solderpaste containing lead or tin, or resin or conductive plastic conductiveepoxy, or a nickel and copper compound. The step of coating metal foilaccording to the present invention has ability of strengthen electricalconnection, but not a necessary step.

[0041] After electrically connecting the connecting pads 111 and theconductive circuits 221, FIG. 8 shows removing the second layer 212 ofthe metal late 200. Generally, method of grinding is used to remove thesecond layer 212 until expose the first layer 211 of conductive circuit221, and isolate different conductive circuits 221 not to shortelectrical connection. In this time, conductive circuits 221 is fixed byadhesive 300.

[0042]FIG. 9 shows plating solder balls 227 or solder bumpers on thesecond ends 223 of conductive circuits 221. Currently, well-knownmethods to form solder balls or solder bumps is evaporation,electroplating or printing. After producing a packed wafer, use dicingfacility 400 to dice along dice area 120 and result in a plurality ofchip size packages as shown in FIG. 10. Or, eliminate step of plantingsolder balls 277 and skip to step of dicing, then result in chip sizepackages secured by solder paste without solder balls.

[0043] Therefore, the method for manufacturing wafer level chip sizepackage according to the present invention is possessed of the followingbenefits. 1) Providing a method for packaging on wafer directly willreduce more manufacturing cost than packaging on chip. 2) Instead ofusing well-known solder bump and wire-bonding as technical way of innerelectrical connection before package, electrically connecting lead frame(conductive circuits 221) and chip 110 after laser controlled depthdrilling 224 will change the interconnection process after package byplating, CVD, PVD or filling. 3) Using redistribution conductivecircuits 221 as redistribution point of out electrical connection forconnecting pads 111 of wafer 100 will increase distance between outconnection points (the second ends 223), reduce fail during surfacemounting, and can be used in wafer level package having multi I/O ends.

[0044] Meanwhile, a chip size package which is provided according topresent invention, as shown in FIG. 10, comprises: a chip 110 having aplurality of connecting pads 111 formed on its active surface, and thechip 110 being upside-down secured to a lead frame in flip chip typewithout growing solder bumps (i.e. bare chip); a lead frame consistingof a plurality of lead fingers 221, wherein, each lead finger 221comprising at least the first end 222 and the second end 223, whereinthe first ends 222 corresponding to a plurality of connecting pads 111of chip 110, and the second ends 223 connected with solder balls 227 asout connection of the connecting pads 111; and an isolative material(package body) in between lead frame and chip 110, such as adhesive 300which is used to secure chip 110 and lead frame (lead fingers 221) asdescribed in manufacturing method. For the isolative material, If useliquid epoxy compound as package body, than at least fill in betweenactive surface of chip 110 and lead frame, and at least expose thesecond ends 223 of the lead frame and a surface of the first ends 222(shown in FIG. 10). Otherwise, as shown in FIG. 13, if use insulationtape 310 as isolative material in between chip 110 and lead frame (leadfingers 221), than fill in only small quantity of liquid epoxy compoundbetween lead fingers 221. When lead frame and chip 110 is secured byadhesive 300, the first ends 220 correspond to connecting pads 111 ofchip 110 vertically, and the exposed surface of the first end 220 isformed from drilling blind holes, exposing connecting pads 111, then,filling in conductive material 226, so that the first ends 222 iselectrically connected to the connecting pads 111 at vertical position.Therefore, the method for chip size package according to the presentinvention is mainly to proceed inner electrical connecting afterpackaging. Steps to drill blind holes on the metal plate, fillconductive material into blink holes, and electrically connect betweenlead fingers 221 and chip 110 replace using bumps and bonding wire asinner electrical connection of a chip during the packaging. Properdistribution of the lead fingers 221 makes the minimum distance ofplurality of second ends 223 being longer than the minimum distance ofthe plurality of first ends 222, and reaching the requirement ofredistribution.

[0045] Secure said chip size package structure to circuit board 500 asshown in FIG. 11. Provide a underfill 510 in between chip size packagestructure and circuit board 500, wherein, the underfill 510 is made fromthermosetting liquid epoxy compound. During re-flowing, uses solderballs to electrically connect between the second ends 223 of the packagestructure and circuit board 500, and solidify underfill simultaneously.For inner electrical connection of the chip size package producing bydrilling blind holes and filling conductive material 226 into the blindholes, chip 110 in the chip size package structure has the ability ofpeeling off. FIG. 12 shows a chip 110 can be peeled off and re-packagedno matter because of the chip 110 being secured to a bad packagestructure (lead frame) or the chip size package structure being securedto a bad circuit board.

[0046] Besides, the method for wafer level chip size package accordingto present invention also provides a process for growing bumps on awafer 100 in a packaged structure, wherein the bump is made from tincompound or gold similar to said solder balls 227 of wafer level chipsize package. The pocess has the benefits of 1) proper protection towafer, 2) packaging wafer of different distribution of connecting padsredistribution and proceeding redistribution of outer connection.

[0047] Although the preferred embodiments of the invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

What is claimed is:
 1. A method for manufacturing wafer level chip sizepackage at least comprising the steps of: providing a wafer having aplurality of chips, each chip having a plurality of connecting pads onits active surface; providing a metal plate consisting of the firstlayer and the second layer, wherein, a plurality of conductive circuitsbeing formed by selectively etching the first layer of the metal plate,the plurality of conductive circuits being fixed on the second layer ofthe metal plate, and individual conductive circuit having at least thefirst end and the second end, and the first ends corresponding to theconnecting pads of chips in the wafer; securing active surface of thewafer to the first layer of the metal plate, when the wafer and themetal plate being secured, connecting pads of the chips and the firstends of the conductive circuits being in vertical position to eachother; drilling blind holes on the plurality of first ends, wherein theblind holes traversing metal plate and extending transversely to exposeconnecting pads of the wafer; filling conductive material on theplurality of blind holes until the connecting pads of chip and the firstends of the conductive circuits becoming electrical connection; removingthe second layer of the metal plate; and dicing the packed wafer andresulting in a plurality of chip size packages.
 2. The method formanufacturing a wafer level chip size package in accordance with claim1, wherein, after the step of removing the second layer of the metalplate, further comprises: planting solder balls on the second ends ofthe conductive circuits.
 3. The method for manufacturing a wafer levelchip size package in accordance with claim 1, wherein, before the stepof filling conductive material, further comprises coating metal foilinside said blind holes.
 4. The method for manufacturing a wafer levelchip size package in accordance with claim 1, wherein in step ofproviding a metal plate, the surface of the first layer of metal plateis rough.
 5. The method for manufacturing a wafer level chip sizepackage in accordance with claim 1, wherein the minimum distance betweena plurality of the second ends is longer than the minimum distancebetween a plurality of the first ends.
 6. The method for manufacturing awafer level chip size package in accordance with claim 1, whereindiameter of the blind hole is smaller than cross sectional diameter ofthe first end.
 7. A chip size package structure comprises: a chip havinga plurality of connecting pads on its active surface and being securedto a lead frame upside down; a lead frame consisting a plurality of leadfingers, wherein each lead finger comprising at least the first end andthe second end, wherein the first ends corresponding to a plurality ofconnecting pads, and the second ends using as outer connection of theconnecting pads; an isolating material sticking the lead frame on theactive surface of the chip so as that the first ends of lead framecorresponding to connecting pads of chip in vertical position; and aplurality of blind holes exposing the connecting pads for electricalconnection of the first end and the connecting pad in the verticalposition.
 8. The chip size package in accordance with claim 7, furthercomprising a metal film inside the blind hole.
 9. The chip size packagein accordance with claim 7, further comprising a conductive material onthe blind hole.
 10. The chip size package in accordance with claim 7,further comprising a plurality of solder balls on the second ends oflead frame.
 11. The chip size package in accordance with claim 7,wherein the said isolating material is a polyimide tape.
 12. The chipsize package in accordance with claim 7, wherein, the minimum distancebetween a plurality of the second ends is longer than the minimumdistance between a plurality of the first ends.
 13. A process forgrowing solder bumps on a wafer, the step comprise: providing a wafercomprising a plurality of chips, each chip having a plurality ofconnecting pads on its active surface; providing a lead frame comprisinga plurality of conductive lead fingers, and each conductive lead fingerat least comprising the first end and the second end, wherein the firstend corresponding to the distribution of connecting pads of chip in thewafer; mechanically securing the said wafer with the lead frame, whenthe wafer and the lead frame being secured, connecting pads of chip andthe corresponding first end of the conductive lead finger being invertical position; laser drilling blind holes on the plurality of firstends, wherein the blind holes traversing metal plate and extendingtransversely to expose connecting pads of the wafer; electricallyconnecting the connecting pads and the corresponding first ends; andplanting a plurality of bumps on the plurality of second ends ofconductive lead fingers.
 14. The process for growing solder bumps on awafer in accordance with claim 13, wherein the step of electricallyconnecting the first end and connecting pad is filling a metal foilinside the blind hole.
 15. The process for growing solder bumps on awafer in accordance with claim 13, wherein the step of electricallyconnecting the first end and connecting pad is coating a conductive filminside the blind hole.
 16. The process for growing solder bumps on waferin accordance with claim 15, wherein the method of coating a conductivefilm inside the blind hole is plating, CVD, or PVD deposition.